1. Field of the Invention
The present invention relates to a method of fabricating a vertical split gate flash memory cell, particularly, a vertical split gate flash memory cell buried in a silicon substrate, with characteristics of high coupling ratio, high density and low programming voltage.
2. Background of the Invention
For the past decade, electrically erasable programmable read only memory (EEPROM) devices have been one of the most popular and well-developed memory devices in the semiconductor industry. The advantages of the EEPROM over a conventional ROM device are its ability to electrically write, save and erase data.
Please refer to FIG. 1 of a cross-sectional conventional split gate flash memory cell 30. As shown in FIG. 1, the conventional split gate flash memory cell 30 comprises a gate oxide layer 32, a floating gate 34, a control gate 38, a drain 42, and a source 44. The control gate 38 is a step structure whereby its lower step end controls a selective channel 31. The upper end of the step structure of the control gate 38 is formed atop the floating gate 34 with a dielectric layer 36, usually of oxide-nitride-oxide (ONO), separating the two gates 34,38.
The flash memory device 30 is programmed when hot electrons from the selective channel 31 are injected into the floating gate 14 by tunneling, via the gate oxide layer 32, according to scattering or other physical mechanisms to thereby increase the threshold voltage of the flash memory cell 30. Erasure occurs when a negative voltage is applied to the control gate 38 to expel the electrons trapped in the floating gate 34. After the electrons are expelled, the threshold voltage of the flash memory cell 30 is restored to its original condition.
Although the split gate flash memory cell solves the problem of over erasing in the conventional flash memory device, the coupling ratio of the split gate flash memory cell is insufficient, leading to a reduced erasing speed or incomplete erasure. Moreover, high-speed, compact, and energy-efficient electronic devices are continually demanded by customers. To satisfy such demands, many types of high-speed/density flash memory devices have been disclosed. For example, a planar step-structure split gate flash memory cell has been developed which involves the use of both an ultra short channel and a ballistic channel hot electrons (CHE) mechanism with the advantages of low program voltage and low energy consumption.
Please refer to FIG. 2 of a cross-section of a conventional step-structure split gate device 50. As shown in FIG.2, the step-structure split gate device 50 comprises a control gate 58 and a floating gate 54 located on a silicon substrate 60. The floating gate 54 is located on a step structure, and includes a horizontal channel of 25 nm in length and a vertical channel of 25 nm in depth. A gate oxide layer 52 of 9 nm thick is positioned between the control gate 58 and the silicon substrate 60, as well as between the floating gate 54 and the silicon substrate 60. An N.sup.+ source region 64 is formed adjacent to the control gate 58 on the surface of the silicon substrate 60, and an N.sup.+ drain region 62 is located adjacent to the floating gate 54 on the surface of the silicon substrate 60. An N-type extended region 63 is located beneath the floating gate 54 adjacent to the N.sup.+ drain region 62, and a P-type doped area 65 is formed at the bend of the step structure to provide a high field region. Hot electrons 71 enter the depleted high field region at one end of the channel beneath the control gate 58, and directly travel towards the floating gate 54. During the injection of the hot electrons 71 into the floating gate 54, either the Coulomb effect or phonon scattering rarely occurs.
In U.S. Pat. No. 6,074,914, Ogura invents a method of making a sidewall split gate flash memory cell which possesses the high speed CHE programming feature, whereby a short channel of 25 to 60 nm is used. In U.S. Pat. No. 6,133,098, Ogura et al. present a method of making a high-density sidewall split gate flash memory cell, which includes the following features:
(1) use of a high density dual-bit cell; PA0 (2) use of the ballistic CHE mechanism, to allow for a low writing current and low writing voltage; and PA0 (3) a third level polysilicon control gate to override coupling of a word line with a floating gate.
However, the conventional photolithographic process makes difficult the manufacturing of a sidewall floating gate with an ultra short channel of 50 nm long. Therefore, a polysilicon layer is generally etched with a reactive ion etching method to form the polysilicon sidewall floating gate along the sidewall of the control gate. By the use of this method, the thickness of the base portion of the floating gate, also called the floating gate channel, is not easily regulated.